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| MC100EPT24 3.3V LVTTL/LVCMOS to Differential LVECL Translator Description The MC100EPT24 is a LVTTL/LVCMOS to differential LVECL translator. Because LVECL levels and LVTTL/LVCMOS levels are used, a -3.3 V, +3.3 V and ground are required. The small outline 8-lead package and the single gate of the EPT24 makes it ideal for those applications where space, performance, and low power are at a premium. Features 8 1 http://onsemi.com MARKING DIAGRAMS* 8 SOIC-8 D SUFFIX CASE 751 1 8 8 1 TSSOP-8 DT SUFFIX CASE 948R 1 DFN8 MN SUFFIX CASE 506AA KA24 ALYWG G KPT24 ALYW G * * * * * * * 1 A L Y W M G = Assembly Location = Wafer Lot = Year = Work Week = Date Code = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. (c) Semiconductor Components Industries, LLC, 2006 December, 2006 - Rev. 8 1 Publication Order Number: MC100EPT24/D 3U MG G 4 350 ps Typical Propagation Delay Maximum Input Clock Frequency > 1.0 GHz Typical The 100 Series Contains Temperature Compensation Operating Range: VCC = 3.0 V to 3.6 V; VEE = -3.6 V to -3.0 V; GND = 0 V PNP LVTTL Input for Minimal Loading Q Output will Default HIGH with Input Open Pb-Free Packages are Available MC100EPT24 Table 1. PIN DESCRIPTION PIN Q, Q 7 LVECL NC 3 6 Q Q D VCC GND VEE NC NC 4 5 GND EP FUNCTION Differential LVECL Outputs LVTTL Input Positive Supply Ground Negative Supply No Connect Exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply or leave floating open. VEE 1 LVTTL 8 VCC D 2 Figure 1. 8-Lead Pinout (Top View) and Logic Diagram Table 2. ATTRIBUTES Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Pb Pkg Level 1 Level 1 Level 1 Value N/A N/A > 4 kV > 200 V > 2 kV Pb-Free Pkg Level 1 Level 3 Level 1 Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) SOIC-8 TSSOP-8 DFN8 Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 in 181 Devices http://onsemi.com 2 MC100EPT24 Table 3. MAXIMUM RATINGS Symbol VCC VEE VIN Iout TA Tstg qJA qJC qJA qJC qJA Tsol Parameter Positive Power Supply Negative Power Supply Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Thermal Resistance (Junction-to-Ambient) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm Standard Board 0 lfpm 500 lfpm Standard Board 0 lfpm 500 lfpm SOIC-8 SOIC-8 SOIC-8 TSSOP-8 TSSOP-8 TSSOP-8 DFN8 DFN8 Condition 1 GND = 0 V GND = 0 V GND = 0 V Continuous Surge Condition 2 VEE = -3.3V VCC = 3.3V VI v VCC Rating 3.8 -3.8 0 to VCC 50 100 -40 to +85 -65 to +150 190 130 41 to 44 185 140 41 to 44 129 84 265 265 Unit V V V mA mA C C C/W C/W C/W C/W C/W C/W C/W C/W C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 4. LVTTL INPUT DC CHARACTERISTICS VCC = 3.3 V, VEE = -3.6 V to -3.0 V, GND = 0.0 V; TA = -40C to 85C Symbol IIH IIHH IIL VIK VIH VIL Characteristic Input HIGH Current Input HIGH Current HIGH Voltage Input LOW Current Input Clamp Voltage Input HIGH Voltage Input LOW Voltage Condition VIN = 2.7 V VCC = VIN = 3.8 V VIN = 0.5 V IIN = -18 mA 2.0 0.8 Min Typ Max 20 100 -0.6 -1.0 Unit mA mA mA V V V NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. Table 5. NECL OUTPUT DC CHARACTERISTICS VCC = 3.3 V, VEE = -3.3 V, GND = 0.0 V (Note 2) -40C Symbol VOH VOL ICC IEE Characteristic Output HIGH Voltage (Note 3) Output LOW Voltage (Note 3) Positive Power Supply Current Negative Power Supply Current 20 Min -1145 -1945 Typ -1020 -1820 2.0 30 Max -895 -1695 4.0 38 20 Min -1145 -1945 25C Typ -1020 -1820 2.0 30 Max -895 -1695 4.0 38 20 Min -1145 -1945 85C Typ -1030 -1820 2.0 30 Max -895 -1695 4.0 38 Unit mV mV mA mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Output levels will vary 1:1 with GND. VEE can vary 0.3 V. 3. Outputs are terminated through a 50 W resistor to GND - 2 V. http://onsemi.com 3 MC100EPT24 Table 6. AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 4) -40C Symbol fmax tPLH, tPHL tJITTER tr tf Characteristic Maximum Input Clock Frequency (Figure 2) Propagation Delay to Output Differential (Note 5) RMS Random Clock Jitter (Figure 2) Output Rise/Fall Times (20% - 80%) @ 50 MHz Q, Q 70 300 Min Typ >1 500 0.2 125 800 <1 170 80 300 Max Min 25C Typ >1 530 0.2 130 800 <1 180 100 300 Max Min 85C Typ >1 560 0.2 150 800 <1 200 Max Unit GHz ps ps ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Measured using a LVTTL source, 50% duty cycle clock source. All loading with 50 W to GND - 2.0 V. 5. Specifications for standard TTL input signal. 900 800 OUTPUT VOLTAGE AMPLITUDE (mV) 700 600 500 400 300 200 (JITTER) 100 9 RMS RANDOM CLOCK JITTER (ps) 8 7 6 5 4 3 2 1 EEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEE EE 0 100 300 500 700 900 1100 1300 INPUT CLOCK FREQUENCY (MHz) Figure 2. Output Voltage Amplitude (VOUTpp)/RMS Jitter vs. Input Clock Frequency at Ambient Temperature Q Driver Device Q Zo = 50 W D Receiver Device Zo = 50 W 50 W 50 W D VTT VTT = VCC - 2.0 V Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.) http://onsemi.com 4 MC100EPT24 ORDERING INFORMATION Device MC100EPT24D MC100EPT24DG MC100EPT24DR2 MC100EPT24DR2G MC100EPT24DT MC100EPT24DTG MC100EPT24DTR2 MC100EPT24DTR2G MC100EPT24MNR4 MC100EPT24MNR4G Package SOIC-8 SOIC-8 (Pb-Free) SOIC-8 SOIC-8 (Pb-Free) TSSOP-8 TSSOP-8 (Pb-Free) TSSOP-8 TSSOP-8 (Pb-Free) DFN8 DFN8 (Pb-Free) Shipping 98 Units / Rail 98 Units / Rail 2500 / Tape & Reel 2500 / Tape & Reel 100 Units / Rail 100 Units / Rail 2500 / Tape & Reel 2500 / Tape & Reel 1000 / Tape & Reel 1000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices http://onsemi.com 5 MC100EPT24 PACKAGE DIMENSIONS SOIC-8 NB CASE 751-07 ISSUE AH -X- A 8 5 B 1 S 4 0.25 (0.010) M Y M -Y- G K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 C -Z- H D 0.25 (0.010) M SEATING PLANE N X 45 _ 0.10 (0.004) M J ZY S X S DIM A B C D G H J K M N S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 MC100EPT24 PACKAGE DIMENSIONS TSSOP-8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R-02 ISSUE A 8x K REF 0.10 (0.004) M 0.15 (0.006) T U S 2X TU S V S L/2 8 1 5 L PIN 1 IDENT 4 B -U- 0.25 (0.010) M 0.15 (0.006) T U S A -V- F DETAIL E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_ C 0.10 (0.004) -T- SEATING PLANE D G DETAIL E -W- DIM A B C D F G K L M http://onsemi.com 7 MC100EPT24 PACKAGE DIMENSIONS DFN8 CASE 506AA-01 ISSUE D D A B PIN ONE REFERENCE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e K L MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.70 0.90 0.50 BSC 0.20 --- 0.25 0.35 2X 0.10 C 2X 0.10 C 0.10 C 8X 0.08 C SEATING PLANE A1 e/2 1 8X 4 L K ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative CCC CCC CCC CCC 8 E TOP VIEW A (A3) C e SIDE VIEW D2 E2 5 8X b 0.10 C A B 0.05 C NOTE 3 BOTTOM VIEW http://onsemi.com 8 MC100EPT24/D |
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